Semiconductor device

ABSTRACT

In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed. A first wiring and a second wiring are laid out as a first metal layer in the memory cell that includes a first inverter and a second inverter. The first wiring is connected with two drains in the first inverter and a second gate wiring in the second inverter. The second wiring is connected with two drains in the second inverter and a first gate wiring in the first inverter. The first wiring is laid out to overlap with the second gate wiring, and the second wiring is laid out to overlap with the first gate wiring. A second metal layer is laid out above the first metal layer, and a third metal layer is laid out above the second metal layer.

CROSS-REFERENCE OF THE INVENTION

This application claims priority from Japanese Patent Application No.2010-182162, the content of which is incorporated herein by reference inits entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor device, specifically to alayout of a semiconductor device provided with a memory cell thatincludes CMOS inverters.

2. Description of the Related Art

In recent years, many computer systems are incorporated in homeappliances and machines, which increasingly require electronic control.A memory-embedded semiconductor device in which a memory such as a flashmemory, SRAM (Static Random Access Memory) or the like is formed on asingle semiconductor substrate (that is, a semiconductor die) togetherwith a microcomputer is known as an example of such a computer system.

In order to reduce a size of the memory-embedded semiconductor device,it is required that an area of the die occupied by the SRAM which isoften primarily used as a buffer memory is decreased as much as possiblewhile an area of the die occupied by the flash memory which is requiredto have a large storage capacity is increased as much as possible.

For example, a memory cell shown in FIG. 1 of Japanese Patent No.4190242 discloses a layout to minimize an area of an SRAM memory cellthat includes two CMOS inverters. In the memory cell, gate wirings ofthe two CMOS inverters are placed close to each other and a connectionbetween drains of transistors in each of the two inverters and a loopconnection between the drains and gates of the two inverters are madeusing two metal layers that are upper layers of the gate wirings. Thearea of the memory cell can be minimized with the layout.

In some cases, however, restrictions to be explained below are imposedin forming the SRAM described above, depending on process technologiesand design rules adopted. The restrictions would increase the area ofthe memory cell and increase the size of the memory-embeddedsemiconductor device in which the SRAM is formed.

For example, in order to optimize manufacturing of the flash memory thatoccupies a large area, process technologies (process technologies forthe flash memory, for example) that are not best suitable formanufacturing the SRAM are adopted in some cases. Since the design rulesare restricted due to conditions of the process technologies and aleakage current is apt to be caused between a source and a draindepending on a width of the gate wiring that constitutes the CMOSinverter in the SRAM, using a layout that requires increased width ofthe gate wiring (that is, gate length) is necessary to suppress theleakage current.

Also, there are cases in which flexibility in designing a wiring patternin an uppermost metal layer is severely restricted, depending on designrules applied to metal layers used in multi-layer wirings. For example,when the design rules impose a restriction that a thick externalconnection electrode such as a bonding pad is to be formed of theuppermost metal layer, fine wiring pattern is not available with theuppermost metal layer.

To explain the restrictions in the design rules in the case where theyare applied to the memory cell of the SRAM shown in FIG. 1 of JapanesePatent No. 4190242, a bit line has to be laid out in a second metallayer that allows fine wiring pattern although it should be otherwiselaid out in the uppermost metal layer that is a third metal layer. Thewiring connecting between the drains of transistors in each of the twoCMOS inverters is also laid out in the second metal layer, and has to belaid out largely detoured to avoid the bit line in the same metal layer.Therefore, the layout of the second metal layer is largely expanded toincrease the area of the memory cell.

This invention is directed to offer a semiconductor device that cansuppress the increase in the area of the memory cell even though thereare restrictions on the gate wiring due to the leakage current betweenthe source and the drain of the transistor in the CMOS inverterconstituting the SRAM or the restrictions in the design rules imposed onthe metal layers used in the multi-layer wiring.

SUMMARY OF THE INVENTION

The invention provides a memory cell configured to operate as part of asemiconductor device. The memory includes a first CMOS inverter having afirst transistor of a P channel and a second transistor of an N channel,a second CMOS inverter having a third transistor of a P channel and afourth transistor of an N channel, a first gate wiring connecting a gateof the first transistor and a gate of the second transistor, a secondgate wiring connecting a gate of the third transistor and a gate of thefourth transistor and a first metal layer disposed on the first andsecond gate wirings and including a first wiring portion and a secondwiring portion. The first wiring portion is connected to a drain of thefirst transistor, a drain of the second transistor and the second gatewiring. The second wiring portion is connected to a drain of the thirdtransistor, a drain of the fourth transistor and the first gate wiring.The first wiring portion overlaps the second gate wiring at leastpartially. The second wiring portion overlaps the first gate wiring atleast partially. The memory cell also includes a second metal layerdisposed on the first metal layer, and a third metal layer disposed onthe second metal layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing an outline structure of a semiconductordevice according to an embodiment of this invention.

FIG. 2 is an equivalent circuit diagram showing a memory cell of an SRAMshown in FIG. 1.

FIG. 3 is a plan view showing a layout of the memory cell of the SRAMshown in FIG. 1.

FIG. 4 is a plan view showing a layout of the memory cell of the SRAMshown in FIG. 1.

FIG. 5 is a plan view showing a layout of the memory cell of the SRAMshown in FIG. 1.

FIG. 6 is a plan view showing a layout of the memory cell of the SRAMshown in FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

A semiconductor device according to an embodiment of this invention willbe described referring to the drawings. FIG. 1 is a plan view showing anoutline structure of the semiconductor device. A static typesemiconductor memory (hereafter referred to as an SRAM 1) made of aregular array of a plurality of memory cells 1A is disposed on asemiconductor substrate 100, as shown in FIG. 1. Also, a flash memory 2and a microcomputer 3 that controls the SRAM 1 and the flash memory 2are disposed on the semiconductor substrate 100. They form amemory-embedded semiconductor device, which is a single semiconductorchip.

The flash memory 2 serves as a large storage capacity (4 M bytes, forexample) memory compared with the SRAM 1 that serves as a small storagecapacity (256 K bytes, for example) buffer memory. In this case, a ratioof an area occupied by the flash memory 2 to a total area of thesemiconductor substrate 100 (about 90%, for example) is significantlylarger than a ratio of an area occupied by the SRAM 1.

An equivalent circuit of the memory cell 1A included in the SRAM 1 ishereafter explained. FIG. 2 is an equivalent circuit diagram showing asingle memory cell 1A out of the plurality of memory cells 1A includedin the SRAM 1.

As shown in FIG. 2, the memory cell 1A includes a first inverter IV1 anda second inverter IV2 that are CMOS inverters and two transfer gates T5and T6 that are made of N channel transistors. The first inverter IV1 iscomposed of a P channel transistor T1 and an N channel transistor T2,and the second inverter IV2 is composed of a P channel transistor T3 andan N channel transistor T4.

The first inverter IV1 and the second inverter IV2 are connected betweena power supply Vcc and a ground, and are always provided with the powersupply Vcc. The inverters IV1 and IV2 are connected to each other toform a loop connection, and connecting nodes ND1 and ND2 retain storeddata that are reverse to each other in a logic level.

An example layout of the memory cell 1A on the semiconductor substrate100 is described below. Each of FIGS. 3 through 6 is a plan view showingdifferent layers in the layout of the memory cell 1A.

FIG. 3 shows a layout of the P channel transistors T1 and T3 and the Nchannel transistors T2 and T4 formed on the semiconductor substrate 100.For example, the P channel transistors T1 and T3 in the first and secondinverters IV1 and IV2 are disposed in an N type well NW disposed in thesemiconductor substrate 100. Each of the P channel transistors T1 and T3has a drain D and a source S that are laid out as a P type active layer.The N channel transistors T2 and T4 in the first and second invertersIV1 and IV2 are disposed in an area of the P type semiconductorsubstrate 100. Each of the N channel transistors T2 and T4 has a drain Dand a source S that are laid out as an N type active layer.

A gate G of the P channel transistor T1 and a gate G of the N channeltransistor T2, which constitute the first inverter IV1, are continuouslyformed as a first gate wiring GL1 that is made of polysilicon. A centerline of the first gate wiring GL1 extends approximately along an Xdirection shown in FIG. 3.

Similarly, a gate G of the P channel transistor T3 and a gate G of the Nchannel transistor T4, which constitute the second inverter IV2, arecontinuously formed as a second gate wiring GL2 that is made ofpolysilicon. A center line of the second gate wiring GL2 also extendsapproximately along the X direction shown in FIG. 3.

In addition, a gate G of the transfer gate T5 and a gate G of thetransfer gate T6 are continuously formed as a word line WL that is madeof polysilicon. A center line of the word line WL extends approximatelyalong a Y direction that orthogonally intersects the X direction asshown in FIG. 3.

The first inverter IV1 and the second inverter IV2 are disposed as closeas possible by laying out as described below.

The drain D of the P channel transistor Ti of the first inverter IV1 islaid out so as to overlap with a line connecting between the drain D ofthe P channel transistor T3 and the drain D of the N channel transistorT4 of the second inverter IV2 and to extend toward the channel beyond aline connecting between a channel side edge of the drain D of the Pchannel transistor T3 and a channel side edge of the drain D of the Nchannel transistor T4. The second gate wiring GL2 is laid out beingpartially bent so that it is separated from the drain D of the P channeltransistor T1. Furthermore, it is preferable that the drain D of the Pchannel transistor T3 is laid out so as to overlap with an extension ofthe center line of the first gate wiring GL1.

On the other hand, the drain D of the N channel transistor T4 of thesecond inverter IV2 is laid out so as to overlap with a line connectingbetween the drain D of the P channel transistor T1 and the drain D ofthe N channel transistor T2 of the first inverter IV1 and to extendtoward the channel beyond a line connecting a channel side edge of thedrain D of the P channel transistor T1 and a channel side edge of thedrain D of the N channel transistor T2. The first gate wiring GL1 islaid out being partially bent so that it is separated from the drain Dof the N channel transistor T4.

With the layout described above, the first inverter IV1 and the secondinverter IV2 can be disposed as close as possible to each other sincethe first gate wiring GL1 and the second gate wiring GL2 can be disposedas close as possible to each other.

A layout of a first metal layer that is an upper layer of the first gatewiring GL1 and the second gate wiring GL2 is hereafter explained. FIG. 4shows the layout of the first metal layer disposed on an insulation film(not shown) that covers the first gate wiring GL1 and the second gatewiring GL2. The first metal layer is made of aluminum or alloy includingaluminum, for example. The first metal layer is shown shaded with dotsin FIG. 4.

A first wiring FL1 laid out as the first metal layer is continuouslyformed and electrically connected with the drain D of the P channeltransistor T1 and the drain D of the N channel transistor T2 of thefirst inverter IV1 as well as being electrically connected with thesecond gate wiring GL2.

The first wiring FL1 is connected with plugs pd1, pd2 and pg1 eachformed in a contact hole penetrating through the insulation film (notshown) on each of the drain D of the P channel transistor T1, the drainD of the N channel transistor T2 and a portion of the second gate wiringGL2, respectively.

A major portion of the first wiring FL1 overlaps with the second gatewiring GL2, and a center line of the first wiring FL1 extends along thesame direction as the second gate wiring GL2, that is the X directionshown in FIG. 4. The first wiring FL1 overlaps with the second gatewiring GL2 at least above the gate G of the N channel transistor T4 ofthe second inverter IV2 and above its vicinity. It is preferable that awidth of the first wiring FL1 overlapping with the second gate wiringGL2 is equal to or smaller than a width of the second gate wiring GL2.For example, the width of the second gate wiring GL2 is about 0.4 μm-0.5μm, while the width of the first wiring FL1 overlapping with the secondgate wiring GL2 is about 0.2 μm-0.3 μm.

A second wiring FL2 laid out as the first metal layer is continuouslyformed and electrically connected with the drain D of the P channeltransistor T3 and the drain D of the N channel transistor T4 of thesecond inverter IV2 as well as being electrically connected with thefirst gate wiring GL1 and a drain D of the transfer gate T6.

The second wiring FL2 is connected with plugs pd3, pd4, pg2 and pd6 eachformed in a contact hole penetrating through the insulation film (notshown) on each of the drain D of the P channel transistor T3, the drainD of the N channel transistor T4, a portion of the first gate wiring GL1and the drain D of the transfer gate T6, respectively.

A major portion of the second wiring FL2 overlaps with the first gatewiring GL1, and a center line of the second wiring FL2 extends along thesame direction as the first gate wiring GL1, that is the X directionshown in FIG. 4. The second wiring FL2 overlaps with the first gatewiring GL1 at least above the gates G of the P channel transistor T1 andthe N channel transistor T2 of the first inverter IV1 and above theirvicinity. It is preferable that a width of the second wiring FL2overlapping with the first gate wiring GL1 is equal to or smaller than awidth of the first gate wiring GL1. The width of the first gate wiringGL1 is similar to the width of the second gate wiring GL2, and the widthof the second wiring FL2 overlapping with the first gate wiring GL1 issimilar to the width of the first wiring FL1 overlapping with the secondgate wiring GL2.

As described above, electrical connection between the two drainsincluded in each of the first and second inverters IV1 and IV2 and theloop connection between the first inverter IV1 and the second inverterIV2 are implemented only with the plugs in the contact holes and thefirst metal layer, without using any other metal layer above the firstmetal layer.

Since the first wiring FL1 is laid out to overlap with the second gatewiring GL2 and the second wiring FL2 is laid out to overlap with thefirst gate wiring GL1, there is no need to increase the layout area ofthe first inverter IV1 and the second inverter IV2 significantly inorder to layout the first wiring FL1 and the second wiring FL2. As aresult, the area of the memory cell 1A can be minimized. Especially, alength W of the memory cell 1A in the Y direction as shown in FIG. 4 canbe minimized.

Furthermore, even when the width of the first gate wiring GL 1 and thewidth of the second gate wiring GL2 are increased in order to suppressthe leakage current between the source and the drain of each of the Pchannel transistors T1 and T3 and the N channel transistors T2 and T4,the first wiring FL1 and the second wiring FL2 are laid out efficientlyusing spaces above the firsts gate wiring GL1 and the second gate wiringGL2 where usually no wiring is laid out. Thus, the increase in the areaof the memory cell can be minimized.

In addition to the first wiring FL1 and the second wiring FL2,conductors sm1, sm3, sm2, sm4, sm5 and sm6 are laid out as the firstmetal layer. Each of the conductors sm1, sm3, sm2, sm4, sm5 and sm6 iselectrically connected to each of the sources S of the P channeltransistors T1 and T3, the N channel transistors T2 and T4 and thetransfer gates T6 and T5, respectively. Each of the conductors sm1, sm3,sm2, sm4, sm5 and sm6 is connected with each of plugs ps1, ps3, ps2,ps4, ps5 and ps6 formed in a contact hole penetrating through theinsulation film (not shown) on each of the sources S, respectively.

A layout of a second metal layer that is an upper layer of the firstmetal layer is hereafter explained. FIG. 5 shows the layout of thesecond metal layer disposed on an insulation film (not shown) thatcovers the first wiring FL1 and the second wiring FL2. The second metallayer is made of aluminum or alloy including aluminum, for example. Thesecond metal layer is shown shaded with solid diagonal lines in FIG. 5.

Two third wirings BL1 and BL2 are laid out in the second metal layer asbit lines that are electrically connected with the sources S of thetransfer gates T5 and T6. The third wiring BL1 is electrically connectedwith the source S of the transfer gate T5, while the other third wiringBL2 laid out adjacent the third wiring BL1 is electrically connectedwith the source S of the transfer gate T6. Each of the third wirings BL1and BL2 is connected with each of the plugs psm5 and psm6 formed in acontact hole penetrating through the insulation film (not shown) on eachof the conductors sm5 and sm6 of the first metal layer, respectively. Acenter line of each of the third wirings BL1 and BL2 extendsapproximately along the X direction as shown in FIG. 5.

In addition to the third wirings BL1 and BL2, conductors mm1, mm2, mm3and mm4 are laid out as the second metal layer. Each of the conductorsmm1, mm2, mm3 and mm4 is electrically connected with each of theconductors sm1, sm2, sm3 and sm4 of the first metal layer through eachof the plugs psm1, psm2, psm3 and psm4 formed in a contact holepenetrating through the insulation film (not shown), respectively.

Furthermore, an insulation film (not shown) is disposed to cover thesecond metal layer, and a third metal layer that is an uppermost metallayer is disposed on the insulation film. The third metal layer is madeof aluminum or alloy including aluminum, for example. In some cases,flexibility in wiring patterns of the third metal layer is severelyrestricted, depending on design rules adopted.

It is assumed in this embodiment that the third metal layer is thickerthan the underlying first metal layer and the second metal layer in sucha way that the third metal layer is formed to be about 0.7 μm-0.8 μmthick while the first metal layer and the second metal layer are about0.5 μm-0.6 μm thick, for example, and is restricted by the design rulesso that the third metal layer is laid out only in coarser and largerpatterns than the first metal layer of the second metal layer. In otherwords, it is assumed that wiring patterns as fine as the first wiringFL1, the second wiring FL2 and the third wirings BL1 and BL2 are notallowed with the third metal layer. The restriction is common to thedesign rules which assume that thick external connection electrodes suchas bonding pads are implemented with the third metal layer, for example.

Because of the restriction by the design rules as described above, thethird wirings BL1 and BL2 that are the bit lines are laid out using thesecond metal layer with which fine patterning is allowed.

A layout of the third metal layer is hereafter explained. FIG. 6 showsthe layout of the third metal layer disposed on the insulation film (notshown) that covers the third wirings BL1 and BL2 made of the secondmetal layer. The third metal layer is shown shaded with dashed diagonallines in FIG. 6.

Because of the restriction by the design rules described above, a fourthwiring TL1, a fifth wiring TL2 and a sixth wiring TL3 are laid out withthe third metal layer in coarser and larger wiring patterns than withthe first and second metal layers. The fourth wiring TL1 is a powersupply line to which a power supply electric potential Vcc is applied,and is connected with the source S of each of the P channel transistorsT1 and T3 in the first and second inverters IV1 and IV2. The fifthwiring TL2 is a ground line to which a ground electric potential isapplied, and is connected with the source S of each of the N channeltransistors T2 and T4 in the first and second inverters IV1 and IV2.

The fourth wiring TL1 is connected with each of plugs pmm1 and pmm3formed in a contact hole penetrating through the insulation film (notshown) on each of the conductors mm1 and mm3, respectively. The fifthwiring TL2 is connected with each of plugs pmm2 and pmm4 formed in acontact hole penetrating through the insulation film (not shown) on eachof the conductors mm2 and mm4, respectively. The sixth wiring TL3 iselectrically connected with the word line WL in a region not shown inFIG. 6 in order to reduce electrical resistance of the word line WL thatis made of polysilicon.

Center lines of the fourth, fifth and sixth wirings TL1, TL2 and TL3extend approximately along a direction perpendicular to the direction ofextension of the first gate wiring GL1 and the second gate wiring GL2,that is, along the Y direction as shown in FIG. 6.

A plurality of the memory cells 1A composed of the multi-layer structureof the layout as described above referring to FIG. 3 through FIG. 6 isarrayed at regular intervals in the X direction and in the Y directionto form a regular pattern. Corresponding to the regular pattern, thememory cells 1A adjacent to each other may be mirror-symmetrical to eachother, or may be slightly modified to accommodate a portion shared bythe adjacent memory cells 1A.

With the layout of the memory cell 1A described above, electricalconnection between the two drains D included in each of the first andsecond inverters IV1 and IV2 and the loop connection of the firstinverter IV1 and the second inverter IV2 are implemented with the firstmetal layer (the first wiring FL1 and the second wiring FL2) even in thecase in which the flexibility in the wiring pattern is severelyrestricted by the design rules. Also, even when the width of the firstgate wiring GL1 and the width of the second gate wiring GL2 are requiredto increase in order to suppress the leakage current between the sourceand the drain of each of the transistors, the first metal layer (thefirst wiring FL1 and the second wiring FL2) is laid out efficientlyutilizing the space above the gate wirings GL1 and GL2. As a result, thearea of the memory cell 1A can be minimized.

Particularly in the memory-embedded semiconductor device in which theflash memory 2 and the microcomputer 3 are disposed on the semiconductorsubstrate 100 in addition to the SRAM 1 that is composed of theplurality of memory cells 1A, the increase in the area of the memorycell 1A of the SRAM 1 makes a factor to increase the size of thesemiconductor device. Since the layout of the memory cell 1A of the SRAM1 can be minimized with the semiconductor device according to theembodiment of this invention, the increase in the size of thememory-embedded semiconductor device can be minimized.

It is apparent that this invention is not limited to the embodimentdescribed above, and may be modified within the scope of the invention.

For example, although the SRAM 1, the flash memory 2 and themicrocomputer 3 are disposed on the semiconductor substrate 100 in theembodiment described above, this invention is not limited to the above.For example, this invention may be applied to the case where the flashmemory 2 or the microcomputer 3 is, or both the flash memory 2 and themicrocomputer 3 are, not disposed on the semiconductor substrate 100.Also, this invention may be applied to the case where a device otherthan the flash memory 2 or the microcomputer 3 is disposed on thesemiconductor substrate 100 as long as the SRAM 1 described above isdisposed.

With the semiconductor device according to the embodiment of thisinvention, the increase in the area of the memory cell can be minimizedeven when there is the restriction on the gate wiring due to the leakagecurrent between the source and the drain of the CMOS inverter or therestriction due to the design rules on the metal layer.

What is claimed is:
 1. A memory cell configured to operate as part of asemiconductor device, the memory comprising: a first CMOS invertercomprising a first transistor of a P channel and a second transistor ofan N channel; a second CMOS inverter comprising a third transistor of aP channel and a fourth transistor of an N channel; a first gate wiringconnecting a gate of the first transistor and a gate of the secondtransistor; a second gate wiring connecting a gate of the thirdtransistor and a gate of the fourth transistor; a first metal layerdisposed on the first and second gate wirings and comprising a firstwiring portion and a second wiring portion, the first wiring portionbeing connected to a drain of the first transistor, a drain of thesecond transistor and the second gate wiring, the second wiring portionbeing connected to a drain of the third transistor, a drain of thefourth transistor and the first gate wiring, the first wiring portionoverlapping the second gate wiring at least partially, and the secondwiring portion overlapping the first gate wiring at least partially; asecond metal layer disposed on the first metal layer; and a third metallayer disposed on the second metal layer.
 2. The semiconductor device ofclaim 1, wherein the first wiring portion, the second gate wiring andthe gate of the fourth transistor overlap, the second wiring portion,the first gate wiring and the gate of the first transistor overlap, andthe second wiring portion, the first gate wiring and the gate of thesecond transistor also overlap.
 3. The semiconductor device of claim 2,wherein a width of the first wiring portion is equal to or smaller thana width of the second gate wiring at the gate of the fourth transistor,and a width of the second wiring portion is equal to or smaller than awidth of the first gate wiring at the gates of the first and secondtransistors.
 4. The semiconductor device of claim 1, further comprisinga first bit line, a second bit line, a first transfer gate and a secondtransfer gate, wherein the first bit line and the second bit line arepart of the second metal layer, the first transfer gate is connected tothe first bit line and the first CMOS inverter, and the second transfergate is connected to the second bit line and the second CMOS inverter.5. The semiconductor device of claim 1, further comprising a powersupply line and a ground line, wherein the power supply line and theground line are part of the third metal layer.
 6. The semiconductordevice of claim 1, further comprising a microcomputer that controls thememory cell, the memory cell and the microcomputer being disposed on asingle substrate.
 7. The semiconductor device of claim 6, furthercomprising a flash memory, the flash memory being disposed on the singlesubstrate and being controlled by the microcomputer.